RED Semiconductor
The Edge Intelligence Company
Intelligence is going to be everywhere—homes, cars, pockets, lives.
We’re the processor that makes it possible.
What We Do
Purpose-Built Processing for the Intelligent Physical Edge
RED Semiconductor develops VISC ™ —a revolutionary compute architecture designed for real-time, low-power algorithmic acceleration.
With our proprietary innovations and incorporating RISC-V CPU architecture, VISC dramatically increases performance for edge AI, cryptography, and continuous data processing.
VISC is the constant math engine behind tomorrow’s intelligent systems—small, fast, secure, and scalable.
Why It Matters
The Future Needs a New Kind of Processor
- Instant responses not delayed cloud inference
- Ultra-low power for constrained devices at the edge
- Security built-in not bolted on
- Efficient bandwidth use filter and process before you transmit
accelerates the algorithms that drive intelligence in real time: on the edge, where it matters.
User Cases
Applications of VISC
Smart Energy
Real-time efficiency optimization in generation, distribution and usage
Secure Automotive
In-vehicle edge AI and sensor fusion
Telecommunications
Secure high-bandwidth beam-focused data communications
Healthcare Devices
Always-on processing
Data Center Pre-Processing
Lower power, local inference before hitting the GPU
why RED
Built to Outperform and Built to Last
Making edge intelligence fast is hard. Making it stay fast is harder.
Edge workloads don’t stand still. New models, new kernels, new security requirements, new latency constraints and streams of data that never stop.
VISC is designed for this reality. Rather than pushing work out to separate blocks and paying a management penalty, VISC brings inline flow-control acceleration into the execution path, reducing clock cycles and memory accesses — the real drivers of edge power.
In early testing, VISC delivers up to 100× acceleration on matrix multiply, a foundational kernel for modern AI and signal-processing workloads.
Key Differentiators:
- Up to 100× early matrix-multiply acceleration
- Inline acceleration — optimised execution without CPU burden
- Reduced code size — abstracted instructions compress complex algorithmic work
- RISC-V ecosystem — VISC extends RISC-V, and is designed to be ISA-flexible over time
- Security-ready — built for trusted, real-time processing where data must be protected
Partner With Us
Work With RED
